Subject Grouping: Technology

Pixel detectors have their roots in photography. Up until 50 years ago, every camera contained a roll of film on which images were photochemically recorded with each exposure, after which the completed roll was sent to be “developed” to finally produce eagerly awaited prints a week or so later. For decades, film also played a big part in particle tracking, with nuclear emulsions, cloud chambers and bubble chambers. The silicon chip, first unveiled to the world in 1961, was to change this picture forever.

During the past 40 years, silicon sensors have transformed particle tracking in high-energy physics experiments

By the 1970s, new designs of silicon chips were invented that consisted of a 2D array of charge-collection sites or “picture elements” (pixels) below the surface of the silicon. During the exposure time, an image focused on the surface generated electron–hole pairs via the photoelectric effect in the underlying silicon, with the electrons collected as signal information in the pixels. These chips came in two forms: the charge-coupled device (CCD) and the monolithic active pixel sensor (MAPS) – more commonly known commercially as the CMOS image sensor (CIS). Willard Boyle and George Smith of Bell Labs in the US were awarded the Nobel Prize for Physics in 2009 for inventing the CCD. 

In a CCD, the charge signals are sequentially transferred to a single on-chip output circuit by applying voltage pulses to the overlying electrode array that defines the pixel structure. At the output circuit the charge is converted to a voltage signal to enable the chip to interface with external circuitry. In the case of the MAPS, each pixel has its own charge-integrating detection circuitry and a voltage signal is again sequentially read out from each by on-chip switching or “scanning” circuitry. Both architectures followed rapid development paths, and within a couple of decades had completely displaced photographic film in cameras. 

For the consumer camera market, CCDs had the initial lead, which passed to MAPS by about 1995. For scientific imaging, CCDs are preferred for most astronomical applications (most recently the 3.2 Gpixel optical camera for the Vera Rubin Observatory), while MAPS are the preferred option for fast imaging such as super-resolution microscopy, cryoelectron microscopy and pioneering studies of protein dynamics at X-ray free-electron lasers. Recent CMOS imagers with very small, low-capacitance pixels achieve sufficiently low noise to detect single electrons. A third member of the family is the hybrid pixel detector, which is MAPS-like in that the signals are read out by scanning circuitry, but in which the charges are generated in a separate silicon layer that is connected, pixel by pixel, to a readout integrated circuit (ROIC). 

During the past 40 years, these devices (along with their silicon-microstrip counterparts, to be described in a later issue) have transformed particle tracking in high-energy physics experiments. The evolution of these device types is intertwined to such an extent that any attempt at historical accuracy, or who really invented what, would be beyond the capacity of this author, for which I humbly apologise. Space constraints have also led to a focus on the detectors themselves, while ignoring the exciting work in ROIC development, cooling systems, mechanical supports, not to mention the advanced software for device simulation, the simulation of physics performance, and so forth. 

CCD design inspiration

The early developments in CCD detectors were disregarded by the particle-detector community. This is because gaseous drift chambers, with a precision of around 100 μm, were thought to be adequate for all tracking applications. However, the 1974 prediction by Gaillard, Lee and Rosner that particles containing charm quarks “might have lifetimes measurable in emulsions”, followed by the discovery of charm in 1975, set the world of particle-physics instrumentation ablaze. Many groups with large budgets tried to develop or upgrade existing types of detectors to meet the challenge: bubble chambers became holographic; drift chambers and streamer chambers were pressurised; silicon microstrips became finer-pitched, etc. 

Pixel architectures

Illustrations of a CCD (left), MAPS (middle) and hybrid chip (right). The first two typically contain 1 k × 1 k pixels, up to 4 k × 4 k or beyond by “stitching”, with an active layer thickness (depleted) of about 20 µm and a highly doped bulk layer back-thinned to around 100 µm, enabling a low-mass tracker, even potentially bent into cylinders round the beampipe. 

The CCD (where I is the imaging area, R the readout register, TG the transfer gate, CD the collection diode, and S, D, G the source, drain and gate of the sense transistor) is pixellised in the I direction by conducting gates. Signal charges are shifted in this direction by manipulating the gate voltages so that the image is shifted down, one row at a time. Charges from the bottom row are tipped into the linear readout register, within which they are transferred, all together in the orthogonal direction, towards the output node. As each signal charge reaches the output node, it modulates the voltage on the gate of the output transistor; this is sensed, and transmitted off-chip as an analog signal. 

In a MAPS chip, pixellisation is implemented by orthogonal channel stops and signal charges are sensed in-pixel by a tiny front-end transistor. Within a depth of about 1 µm below the surface, each pixel contains complex CMOS electronics. The simplest readout is “rolling shutter”, in which peripheral logic along the chip edge addresses rows in turn, and analogue signals are transmitted by column lines to peripheral logic at the bottom of the imaging area. Unlike in a CCD, the signal charges never move from their “parent” pixel. 

In the hybrid chip, like a MAPS, signals are read out by scanning circuitry. However, the charges are generated in a separate silicon layer that is connected, pixel by pixel, to a readout integrated circuit. Bump-bonding interconnection technology is used to keep up with pixel miniaturisation. 

The ACCMOR Collaboration (Amsterdam, CERN, Cracow, Munich, Oxford, RAL) had built a powerful multi-particle spectrometer, operating at CERN’s Super Proton Synchrotron, to search for hadronic production of the recently-discovered charm particles, and make the first measurements of their lifetimes. We in the RAL group picked up the idea of CCDs from astronomers at the University of Cambridge, who were beginning to see deeper into space than was possible with photographic film (see left figure in “Pixel architectures” panel). The brilliant CCD developers in David Burt’s team at the EEV Company in Chelmsford (now Teledyne e2v) suggested designs that we could try for particle detection, notably to use epitaxial silicon wafers with an active-layer thickness of about 20 μm. At a collaboration meeting in Cracow in 1978, we demonstrated via simulations that just two postage-stamp-sized CCDs, placed 1 and 2 cm beyond a thin target, could cover the whole spectrometer aperture and might be able to deliver high-quality topological reconstruction of the decays of charm particles with expected lifetimes of around 10^–13 s. 

We still had to demonstrate that these detectors could be made efficient for particle detection. With a small telescope comprising three CCDs in the T6 beam from CERN’s Proton Synchrotron we established a hit efficiency of more than 99%, a track measurement precision of 4.5 μm in x and y, and two-track resolution of 40 μm. Nothing like this had been seen before in an electronic detector. Downstream of us, in the same week, a Yale group led by Bill Willis obtained signals from a small liquid-argon calorimeter. A bottle of champagne was shared! 

It was then a simple step to add two CCDs to the ACCMOR spectrometer and start looking for charm particles. During 1984, on the initial shift, we found our first candidate (see “First charm” figure), which, after adding the information from the downstream microstrips, drift chambers (with two large aperture magnets for momentum measurement), plus a beautiful assembly of Cherenkov hodoscopes from the Munich group, proved to be a D⁺→ K⁺π⁺π^– event. 

It was more challenging to develop a CCD-based vertex detector for the SLAC Large Detector (SLD) at the SLAC Linear Collider (SLC), which became operational in 1989. The level of background radiation required a 25 mm-radius beam pipe, and the physics demanded large solid-angle coverage, as in all general-purpose collider detectors. The physics case for SLD had been boosted by the discovery in 1983 that the lifetime of particles containing b quarks was longer than for charm, in contrast to the theoretical expectation of being much shorter. So the case for deploying high-quality vertex detectors at SLC and LEP, which were under construction to study Z⁰ decays, was indeed compelling (see “Vertexing” figure). All four LEP experiments employed a silicon-microstrip vertex detector.

Early in the silicon vertex-detector programme, e2V perfected the art of “stitching” reticles limited to an area of 2 × 2 cm², to make large CCDs (8 × 1.6 cm² for SLD). This enabled us to make a high-performance vertex detector that operated from 1996 until SLD shut down in 1998, and which delivered a cornucopia of heavy-flavour physics from Z⁰ decays (see “Pioneering pixels” figure). During this time, the LEP beam pipe, limited by background to 54 mm radius, permitted its experiments’ microstrip-based vertex detectors to do pioneering b physics. But it had reduced capability for the more elusive charm, which was shorter lived and left fewer decay tracks. 

Between LEP with its much higher luminosity and SLD with its small beam pipe, state-of-the-art vertex detector and highly polarised electron beam, the study of Z⁰ decays yielded rich physics. Highlights included very detailed studies of an enormous sample of gluon jets from Z⁰ → b b g events, with cleanly tagged b jets at LEP, and A_c, the parity-violation parameter in the coupling of the Z⁰ to c-quarks, at SLD. However, the most exciting discovery of that era was the top quark at Fermilab, in which the SVX microstrip detector of the CDF detector played an essential part (see “Top detector” figure). This triggered a paradigm shift. Before then, vertex detectors were an “optional extra” in experiments; afterwards, they became obligatory in every energy frontier detector system. 

Hybrid devices

While CCDs pioneered the use of silicon pixels for precision tracking, their use was restricted by two serious limitations: poor radiation tolerance and long readout time (tens of ms due to the need to transfer the charge signals pixel by pixel through a single output circuit). There was clearly a need for pixel detectors in more demanding environments, and this led to the development of hybrid pixel detectors. The idea was simple: reduce the strip length of well-developed microstrip technology to equal its width, and you had your pixel sensor. However, microstrip detectors were read out at one end by ASIC (application-specific integrated circuit) chips having their channel pitch matched to that of the strips. For hybrid pixels, the ASIC readout required a front-end circuit for each pixel, resulting in modules with the sensor chip facing the readout chip, with electrical connections made by metal bump-bonds (see right figure in “Pixel architectures” panel). The use of relatively thick sensor layers (compared to CCDs) compensated for the higher node capacitance associated with the hybrid front-end circuit.

Although the idea was simple, its implementation involved a long and challenging programme of engineering at the cutting edge of technology. This had begun by about 1988, when Erik Heijne and colleagues in the CERN microelectronics group had the idea to fit full nuclear-pulse processing electronics in every pixel of the readout chip, with additional circuitry such as digitisation, local memory and pattern recognition on the chip periphery. With a 3 μm feature size, they were obliged to begin with relatively large pixels (75 × 500 μm), and only about 80 transistors per pixel. They initiated the RD19 collaboration, which eventually grew to 150 participants, with many pioneering developments over a decade, leading to successful detectors in at least three experiments: WA97 in the Omega Spectrometer; NA57; and forward tracking in DELPHI. As the RD19 programme developed, the steady reduction in feature size permitted the use of in-pixel discriminators and fast shapers that enhanced the noise performance, even at high rates. This would be essential for operation of large hybrid pixel systems in harsh environments, such as ATLAS and CMS at the LHC. RD19 initiated a programme of radiation hardness by design (enclosed-gate transistors, guard rings, etc), which was further developed and broadly disseminated by the CERN microelectronics group. These design techniques are now used universally across the LHC detector systems. There is still much to be learned, and advances to a smaller feature size bring new opportunities but also surprises and challenges. 

The advantages of the hybrid approach include the ability to choose almost any commercial CMOS process and combine it with the sensor best adapted to the application. This can deliver optimal speed of parallel processing, and radiation hardness as good as can be engineered in the two component chips. The disadvantages include a complex and expensive assembly procedure, high power dissipation due to large node capacitance, and more material than is desirable for a tracking system. Thanks to the sustained efforts of many experts, an impressive collection of hybrid pixel tracking detectors has been brought to completion in a number of detector facilities. As vertex detectors, their greatest triumph has been in the inferno at the heart of ATLAS and CMS where, for example, they were key to the recent measurement of the branching ratio for H → b b . 

Facing up to the challenge

The high-luminosity upgrade to the LHC (HL-LHC) is placing severe demands on ATLAS and CMS, none more so than developing even more powerful hybrid vertex detectors to accommodate a “pileup” level of 200 events per bunch crossing. For the sensors, a 3D variant invented by Sherwood Parker has adequate radiation hardness, and may provide a more secure option than the traditional planar pixels, but this question is still open. 3D pixels have already proved themselves in ATLAS, for the insertable B layer (IBL), where the signal charge is drifted transversally within the pixel to a narrow column of n-type silicon that runs through the thickness of the sensor. But for HL-LHC, the innermost pixels need to be at least five times smaller in area than the IBL, putting extreme pressure on the readout chip. The RD53 collaboration led by CERN has worked for years on the development of an ASIC using 65 nm feature size, which enables the huge amount of radiation-resistant electronics to fit within the pixel area, reaching the limit of 50 × 50 μm². Assembling these delicate modules, and dealing with the thermal stresses associated with the power dissipation in the warm ASICs mechanically coupled to the cold sensor chips, is still a challenge. These pixel tracking systems (comprising five layers of barrel and forward trackers) will amount to about 6 Gpixels – seven times larger than before. Beyond the fifth layer, conditions are sufficiently relaxed that microstrip tracking will still be adequate. 

The latest experiment to upgrade from strips to pixels is LHCb, which has an impressive track record of b and charm physics. Its adventurous Vertex Locator (VELO) detector has 26 disks along the beamline, equipped with orthogonally oriented r and ϕ microstrips, starting from inside the beampipe about 8 mm from the LHC beam axis. LHCb has collected the world’s largest sample of charmed hadrons, and with the VELO has made a number of world-leading measurements including the discovery of CP violation in charm. LHCb is now statistics-limited for many rare decays and will ramp up its event samples with a major upgrade implemented in two stages (see State-of-the-art-tracking for high luminosities).

For the first upgrade, due to begin operation early next year, the luminosity will increase by a factor of up to five, and the additional pattern recognition challenge will be addressed by a new pixel detector incorporating 55 μm pixels and installed even closer (5.1 mm) to the beam axis. The pixel detector uses evaporative CO₂ microchannel cooling to allow operation under vacuum. LHCb will double its efficiency by removing the hardware trigger and reading out the data at the beam-crossing frequency of 40 MHz. The new “VeloPix” readout chip will achieve this with readout speeds of up to 20 Gb/s, and the software trigger will select heavy-flavour events based on full event reconstruction. For the second upgrade, due to begin in about 2032, the luminosity will be increased by a further factor of 7.5, allowing LHCb to eventually accumulate 10 times its current statistics. Under these conditions, there will be, on average, 40 interactions per beam crossing, which the collaboration plans to resolve by enhanced timing precision (around 20 ps) in the VELO pixels. The upgrade will require both an enhanced sensor and readout chip. This is an adventurous long-term R&D programme, and LHCb retain a fallback option with timing layers downstream of the VELO, if required. 

Monolithic active pixels

Being monolithic, the architecture of MAPS is very similar to that of CCDs (see middle figure in “Pixel architectures” panel). The fundamental difference is that in a CCD, the signal charge is transported physically through some centimetres of silicon to a single charge-sensing circuit in the corner of the chip, while in a MAPS the communication between the signal charge and the outside world is via in-pixel electronics, with metal tracks to the edge of the chip. The MAPS architecture looked very promising from the beginning, as a route to solving the problems of both CCDs and hybrid pixels. With respect to CCDs, the radiation tolerance could be greatly increased by sensing the signal charge within its own pixel, instead of transporting it over thousands of pixels. The readout speed could also be dramatically increased by in-pixel amplitude discrimination, followed by sparse readout of only the hit pixels. With respect to hybrid pixel modules, the expense and complications of bump-bonded assemblies could be eliminated, and the tiny node capacitance opened the possibility of much thinner active layers than were needed with hybrids.

MAPS have emerged as an attractive option for a number of future tracking systems. They offer small pixels where needed (notably for inner-layer vertex detectors) and thin layers throughout the detector volume, thereby minimising multiple scattering and photon conversion, both in barrels and endcaps. Excess material in the forward region of tracking systems such as time-projection and drift chambers, with their heavy endplate structures, has in the past led to poor track reconstruction efficiency, loss of tracks due to secondary interactions, and excess photon conversions. In colliders at the energy frontier (whether pp or e⁺e^–), however, interesting events for physics are often multi-jet, so there are nearly always one or more jets in the forward region. 

The first MAPS devices contained little more than a collection diode, a front-end transistor operated as a source follower, reset transistor and addressing logic. They needed only relaxed charge-collection time, so diffusive collection sufficed. Sherwood Parker’s group demonstrated their capability for particle tracking in 1991, with devices processed in the Centre for Integrated Studies at Stanford, operating in a Fermilab test beam. In the decades since, advances in the density of CMOS digital electronics have enabled designers to pack more and more electronics into each pixel. For fast operation, the active volume below the collection diode needs to be depleted, including in the corners of the pixels, to avoid loss of tracking efficiency. 

The Strasbourg group led by Marc Winter has a long and distinguished record of MAPS development. As well as highly appreciated telescopes in test beams at DESY for general use, the group supplied its MIMOSA-28 devices for the first MAPS-based vertex detector: a 356 Mpixel two-layer barrel system for the STAR experiment at Brookhaven’s Relativistic Heavy Ion Collider. Operational for a three-year physics run starting in 2014, this detector enhanced the capability to look into the quark–gluon plasma, the extremely hot form of matter that characterised the birth of the universe. 

Advances in the density of CMOS digital electronics have enabled designers to pack more and more electronics into each pixel

An ingenious MAPS variant developed by the Semiconductor Laboratory of the Max Planck Society – the Depleted P-channel FET (DEPFET) – is also serving as a high-performance vertex detector in the Belle II detector at SuperKEKB in Japan, part of which is already operating. In the DEPFET, the signal charge drifts to a “virtual gate” located in a buried channel deeper than the current flowing in the sense transistor. As Belle II pushes to even higher luminosity, it is not yet clear which technology will deliver the required radiation hardness. 

The small collection electrode of the standard MAPS pixel presents a challenge in terms of radiation hardness, since it is not easy to preserve full depletion after high levels of bulk damage. An important initiative to overcome this was initiated in 2007 by Ivan Perić of KIT, in which the collection electrode is expanded to cover most of the pixel area, below the level of the CMOS electronics, so the charge-collection path is much reduced. Impressive further developments have been made by groups at Bonn University and elsewhere. This approach has achieved high radiation resistance with the ATLASpix prototypes, for instance. However, the standard MAPS approach with small collection electrode may be tunable to achieve the required radiation resistance, while preserving the advantages of superior noise performance due to the much lower sensor capacitance. Both approaches have strong backing from talented design groups, but the eventual outcome is unclear. 

Advanced MAPS

Advanced MAPS devices were proposed for detectors at the International Linear Collider (ILC). In 2008 Konstantin Stefanov of the Open University suggested that MAPS chips could provide an overall tracking system of about 30 Gpixels with performance far beyond the baseline options at the time, which were silicon microstrips and a gaseous time-projection chamber. This development was shelved due to delays to the ILC, but the dream has become a reality in the MAPS-based tracking system for the ALICE detector at the LHC, which builds on the impressive ALPIDE chip development by Walter Snoeys and his collaborators. The ALICE ITS-2 system, with 12.5 Gpixels, sets the record for any pixel system (see ALICE tracks new territories). This beautiful tracker has operated smoothly on cosmic rays and is now being installed in the overall ALICE detector. The group is already pushing to upgrade the three central layers using wafer-scale stitching and curved sensors to significantly reduce the material budget. At the 2021 International Workshop on Future Linear Colliders held in March, the SiD concept group announced that they will switch to a MAPS-based tracking system. R&D for vertexing at the ILC is also being revived, including the possibility of CCDs making a comeback with advanced designs from the KEK group led by Yasuhiro Sugimoto.

The most ambitious goal for MAPS-based detectors is for the inner-layer barrels at ATLAS and CMS, during the second phase of the HL-LHC era, where smaller pixels would provide important advantages for physics. At the start of high-luminosity operation, these layers will be equipped with hybrid pixels of 25 × 100 μm² and 150 μm active thickness, the pixel area being limited by the readout chip, which is based on a 65 nm technology node. Encouraging work led by the CERN ATLAS and microelectronics groups and the Bonn group is underway, and could result in a MAPS option of 25 × 25 μm², requiring an active-layer thickness of only about 20 μm, using a 28 nm technology node. The improvement in tracking precision could be accompanied by a substantial reduction in power dissipation. The four-times greater pixel density would be more than offset by the reduction in operating voltage, plus the much smaller node capacitance. This route could provide greatly enhanced vertex detector performance at a time when the hybrid detectors will be coming to the end of their lives due to radiation damage. However, this is not yet guaranteed, and an evolution to stacked devices may be necessary. A great advantage of moving to monolithic or stacked devices is that the complex processes are then in the hands of commercial foundries that routinely turn out thousands of 12 inch wafers per week. 

High-speed and stacked

During HL-LHC operations there is a need for ultra-fast tracking devices to ameliorate the pileup problems in ATLAS, CMS and LHCb. Designs with a timing precision of tens of picoseconds are advancing rapidly – initially low-gain avalanche diodes, pioneered by groups from Torino, Barcelona and UCSC, followed by other ultra-fast silicon pixel devices. There is a growing list of applications for these devices. For example, ATLAS will have a layer adjacent to the electromagnetic calorimeter in the forward region, where the pileup problems will be severe, and where coarse granularity (~1 mm pixels) is sufficient. LHCb is more ambitious for its stage-two upgrade, as already mentioned. There are several experiments in which such detectors have potential for particle identification, notably π/K separation by time-of-flight up to a momentum limit that depends on the scale of the tracking system, typically 8 GeV/c.

Monolithic and hybrid pixel detectors answer many of the needs for particle tracking systems now and in the future. But there remain challenges, for example the innermost layers at ATLAS and CMS. In order to deliver the required vertexing capability for efficient, cleanly separated b and charm identification, we need pixels of dimensions about 25 × 25 μm, four times below the current goals for HL-LHC. They should also be thinner, down to say 20 μm, to preserve precision for oblique tracks. 

Solutions to these problems, and similar challenges in the much bigger market of X-ray imaging, are coming into view with stacked devices, in which layers of CMOS-processed silicon are stacked and interconnected. The processing technique, in which wafers are bonded face-to-face, with electrical contacts made by direct-bond interconnects and through-silicon vias, is now a mature technology and is in the hands of leading companies such as Sony and Samsung. The CMOS imaging chips for phone cameras must be one of the most spectacular examples of modern engineering (see “Up close” figure). 

Commercial CMOS image sensor development is a major growth area, with approximately 3000 patents per year. In future these developers, advancing to smaller-node chips, will add artificial intelligence, for example to take a number of frames of fast-moving subjects and deliver the best one to the user. Imagers under development for the automotive industry include those that will operate in the short-wavelength infrared region, where silicon is still sensitive. In this region, rain and fog are transparent, so a driverless car equipped with the technology will be able to travel effortlessly in the worst weather conditions. 

While we developers of pixel imagers for science have not kept up with the evolution of stacked devices, several academic groups have over the past 15 years taken brave initiatives in this direction, most impressively a Fermilab/BNL collaboration led by Ron Lipton, Ray Yarema and Grzegorz Deptuch. This work was done before the technical requirements could be serviced by a single technology node, so they had to work with a variety of pioneering companies in concert with excellent in-house facilities. Their achievements culminated in three working prototypes, two for particle tracking and one for X-ray imaging, namely a beautiful three-tier stack comprising a thick sensor (for efficient X-ray detection), an analogue tier and a digital tier (see “Stacking for physics” figure). 

Technology nodes

The relatively recent term “technology node” embraces a number of aspects of commercial integrated circuit (IC) production. First and foremost is the feature size, which originally meant the minimum line width that could be produced by photolithography, for example the length of a transistor gate. With the introduction of novel transistor designs (notably the FinFET), this term has been generalised to indicate the functional density of transistors that is achievable. At the start of the silicon-tracker story, in the late 1970s, the feature size was about 3 µm. The current state-of-the-art is 5 nm, and the downward Moore’s law trend is continuing steadily, although such narrow lines would of course be far beyond the reach of photolithography. There are other aspects of ICs that are included in the description of any technology node. One is whether they support stitching, which means the production of larger chips by step-and-repeat of reticles, enabling the production of single devices of sizes 10 × 10 cm² and beyond, in principle up to the wafer scale (which these days is a diameter of 200 or 300 mm, evolving soon to 450 mm). Another is whether they support wafer stacking, which is the production of multi-layer sandwiches of thinned devices using various interconnect technologies such as through-silicon vias and direct-bond interconnects. A third aspect is whether they can be used for imaging devices, which implies optimised control of dark current and noise. For particle tracking, the most advanced technology nodes are unaffordable (the development cost of a single 5 nm ASIC is typically about $500 million, so it needs a large market). However, other features that are desirable and becoming essential for our needs (imaging capability, stitching and stacking) are widely available and less expensive. For example, Global Foundries, which produces 3.5 million wafers per annum, offers these capabilities at their 32 and 14 nm nodes.

For the HL-LHC inner layers, one could imagine a stacked chip comprising a thin sensor layer (with excellent noise performance enabled by an on-chip front-end circuit for each pixel), followed by one or more logic layers. Depending on the technology node, one should be able to fit all the logic (building on the functionality of the RD53 chip) in one or two layers of 25 × 25 μm pixels. The overall thickness could be 20 μm for the imaging layer, and 6 μm per logic layer, with a bottom layer sufficiently thick (~100 μm) to give the necessary mechanical stability to the relatively large stitched chips. The resulting device would still be thin enough for a high-quality vertex detector, and the thin planar sensor-layer pixels including front-end electronics would be amenable to full depletion up to the 10-year HL-LHC radiation dose.

There are groups in Japan (at KEK led by Yasuo Arai, and at RIKEN led by Takaki Hatsui) that have excellent track records for developing silicon-on-insulator devices for particle tracking and for X-ray detection, respectively. The RIKEN group is now believed to be collaborating with Sony to develop stacked devices for X-ray imaging. Given Sony’s impressive achievements in visible-light imaging, this promises to be extremely interesting. There are many applications (for example at ITER) where radiation-resistant X-ray imaging will be of crucial importance, so this is an area in which stacked devices may well own the future. 

Outlook 

The story of frontier pixel detectors is a bit like that of an art form – say cubism. With well-defined beginnings 50 years ago, it has blossomed into a vast array of beautiful creations. The international community of designers see few boundaries to their art, being sustained by the availability of stitched devices to cover large-area tracking systems, and moving into the third dimension to create the most advanced pixels, which are obligatory for some exciting physics goals. 

Face-to-face wafer bonding is now a commercially mature technology

Just like the attribute of vision in the natural world, which started as a microscopic light-sensitive spot on the surface of a unicellular protozoan, and eventually reached one of its many pinnacles in the eye of an eagle, with its amazing “stacked” data processing behind the retina, silicon pixel devices are guaranteed to continue evolving to meet the diverse needs of science and technology. Will they one day be swept away, like photographic film or bubble chambers? This seems unthinkable at present, but history shows there’s always room for a new idea.