Capturing the data
As shown in figure 4, CMS has chosen to reduce this rate in two steps. At the first level, all data are stored for 3 µs, after which no more than 75 kHz of the stored events are forwarded to the high-level trigger (HLT) system. This must be done for all channels without dead time.
Figure 4 also shows the ATLAS pipelined, deadtimeless, level one trigger system with a latency of 2.5 µs. However, after a level one accept, regions of interest in the data are further analysed by a second level of dedicated hardware processors - which include tracking data - before a rate of events reduced by an order of magnitude are transmitted to the processor farm.
In the case of both CMS and ATLAS, the level one system uses only coarsely segmented data from calorimeter and muon detectors, while holding all of the high-resolution data in pipeline memories in the front-end electronics. During the level one trigger processing time, decisions must be developed that discard the larger portion of the data while retaining the small fraction that relates to interactions of potential significance. The large size of the detector and the short decision time present a series of technical and system challenges.
The ATLAS event filter and the CMS HLT are implemented as processing farms that are designed to achieve a rejection factor of 103 and about 100 events per second to mass storage. The last stage of HLT processing involves reconstruction and event filtering with the primary goal of making datasets of different signatures on easily accessed media for further analysis by the worldwide physics community. A global "grid" network of information systems (see The grid is set to grapple with large computations;June 2000) is already being prepared to absorb this tidal wave of data.
Hardware solutions
The LHC experiments have addressed level one trigger systems with a variety of high-speed hardware. The CMS Calorimeter Level One Regional Trigger uses 160 MHz logic boards plugged into the front and back of a custom backplane, which provides point-to-point links between the cards. Much of the processing in this system is performed by five types of 160 MHz digital applications-specific integrated circuits designed using Vitesse submicron high-integration gallium arsenide gate array technology.
The LHC experiments make extensive use of field programmable gate arrays (FPGAs). These offer programmable reconfigurable logic, which has the flexibility that trigger designers need to be able to alter algorithms so that they can follow the physics and detector performance more closely as luminosity and beam conditions change. As shown in figure 5, during the past decade there has been a remarkable improvement in FPGA speed and capacity, while the price has dropped. The enhanced performance of these devices is resulting in improved level one trigger designs.
Another important industrial development is the advent of high-bandwidth telecoms switches. These devices allow hundreds of buffers of LHC front-end read-out electronics to be connected to the hundreds of computer processing nodes that must analyse the data. The greater the bandwidth of these switches, the more data can be brought directly to the processing nodes for detailed analysis.
The option to have an increasing proportion of commodity hardware in the read-out network and data processing enables more easily scalable and supportable designs, which can be augmented with additional straightforward purchases as more processing power is needed.
Overall, the LEB workshop in Cracow provided an excellent opportunity for the international community of physicists and engineers from the four LHC experiments to review their work in preparing the electronics for constructing working detectors in 2005.
The past six years have seen spectacular progress in developing advanced electronics systems suitable for the challenges of LHC experiments. This has been achieved via collaborative partnerships between industry and the research community.
However, there are many problems that have still to be solved. Obtaining the demanding performance required of these massive and complex electronics systems will require creativity, excellent engineering and the optimal utilization of the very limited resources available. The LEB workshop planned for Stockholm in September 2001 will show the results obtained by that stage.
The workshop held in Cracow was organized by the LHC Electronics Board with the help of CERN, the UK Rutherford Appleton Laboratory and, locally, the Faculty of Physics and Nuclear Techniques of the University of Mining and Metallurgy, and the Institute of Nuclear Physics.